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    • 专利摘要:
    The invention relates to an optoelectronic device (1), comprising: ○ at least one diode (2), comprising a semiconductor portion (20) in which a PN or PIN junction is formed; ○ a peripheral conductive layer (40), extending in the main plane so as to surround the semiconductor portion (20); A peripheral piezoelectric portion (30) extending in the main plane so as to surround the semiconductor portion (20); A first polarization electric circuit (30), adapted to generate an electric field in the peripheral piezoelectric portion (30) by applying an electric potential to at least the peripheral conductive layer (40), so as to induce deformation of the portion peripheral piezoelectric device (30) oriented along the main plane then causing voltage deformation of the semiconductor portion (20) along the main plane.
    公开号:FR3080489A1
    申请号:FR1853386
    申请日:2018-04-18
    公开日:2019-10-25
    发明作者:Abdelkader Aliane；Luc Andre；Jean-Louis Ouvrier-Buffet
    申请人:Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    OPTOELECTRONIC DEVICE WITH A VOLTAGE-CONSTRAINED DIODE BY REVERSE PIEZOELECTRIC EFFECT
    TECHNICAL FIELD The field of the invention is that of optoelectronic devices comprising at least one diode produced on the basis of a voltage-stressed semiconductor compound. The invention finds an application in particular in the field of detection of light radiation belonging for example to the near infrared, the diode (s) of the optoelectronic device then being able to be made based on voltage-constrained germanium.
    STATE OF THE PRIOR ART In various microelectronic or optoelectronic applications, it may be advantageous to use a layer of a crystalline semiconductor compound, preferably monocrystalline, having a mechanical stress in tension. This is the case in particular of certain light sources whose material of the emissive layer has, without stress, a structure of bands of indirect energy, the structure of bands being then made direct by the application of a stress in tension sufficient. The crystalline semiconductor compound can be a germanium-based compound, for example germanium, tin germanium, or even germanium silicon.
    Thus, document US2014 / 0291682 describes an avalanche photodiode, the semiconductor absorption layer of which is made of voltage-stressed germanium. The photodiode is then adapted to absorb light radiation up to a cutoff wavelength greater than 1550nm, which is the cutoff wavelength for absorption of relaxed germanium. For this, the germanium layer is coated with a stress layer formed of a stack of sublayers of silicon nitride, silicon oxide and amorphous silicon. However, this photodiode has the particular disadvantage of being obtained by using engineering techniques of mechanical stress by depositing a stack of thin layers, which can make the manufacturing process complex.
    Document EP3151265 describes an optoelectronic diode device comprising a voltage-constrained semiconductor layer made from germanium. The semiconductor layer was here tensioned by prior localized structuring of the layer, then by suspending the structured layer above a substrate, followed by joining to the latter by direct bonding. Consolidation annealing
    DD18624 - ICG090247 is finally implemented to improve the mechanical resistance of the stress structured layer bonded to the substrate. However, this optoelectronic device has the particular disadvantage of being obtained by a relatively complex manufacturing process. In addition, as in the previous document, controlling the value of the voltage stress actually experienced by the semiconductor layer can be particularly difficult.
    There is therefore a need to have an optoelectronic device whose value of the mechanical stress in voltage undergone by the diode or diodes is controlled in a simpler and more precise manner. There is also a need to have such an optoelectronic device capable of having a reduced bulk and a high spatial resolution when it comprises a matrix of diodes, and capable of being obtained by a simplified manufacturing process.
    PRESENTATION OF THE INVENTION The aim of the invention is to remedy at least in part the drawbacks of the prior art, and more particularly to propose an optoelectronic device comprising one or more diodes which can be energized in an active manner. It also aims to propose an optoelectronic device having a reduced bulk, and capable of being obtained by a simplified manufacturing process. It also aims to propose an optoelectronic device comprising a matrix of diodes with high spatial resolution.
    For this, the object of the invention is an optoelectronic device comprising: o at least one diode, comprising a semiconductor portion having:
    • a first face and a second opposite face, substantially parallel to a main plane, and connected to each other by a lateral border, and • a PN or PIN junction formed by:
    a first region doped according to a first type of conductivity, and a second region doped according to a second type of conductivity opposite to the first type, extending from the lateral border;
    o a peripheral conductive layer, made of at least one electrically conductive material, extending along the main plane in contact with the second doped region so as to surround the semiconductor portion;
    o a peripheral piezoelectric portion, made of at least one piezoelectric material, extending along the main plane in contact with the peripheral conductive layer so as to surround the semiconductor portion;
    DD18624 - ICG090247 a first electrical circuit for biasing the peripheral piezoelectric portion, adapted to generate an electric field in the peripheral piezoelectric portion by applying an electrical potential to at least the peripheral conductive layer, so as to induce deformation of the peripheral piezoelectric portion oriented along the main plane then causing a voltage deformation of the semiconductor portion along the main plane.
    Some preferred but non-limiting aspects of this optoelectronic device are as follows.
    [009] Preferably, the peripheral conductive layer and the peripheral piezoelectric portion surround the semiconductor portion continuously.
    Preferably, the peripheral conductive layer fully covers the lateral border of the semiconductor portion along an axis orthogonal to the main plane, and the peripheral piezoelectric portion fully covers the peripheral conductive layer along said orthogonal axis.
    Preferably, the side border extends substantially orthogonal to the main plane.
    The peripheral piezoelectric portion may have a thickness at least equal to that of the semiconductor portion.
    The optoelectronic device may include a second electrical circuit, for biasing the diode, adapted to apply said electrical potential to the second doped region through the peripheral conductive layer and a different electrical potential to the first doped region.
    The first doped portion can extend from the first face and is distant from the side border.
    The diode may include:
    a PIN junction, the first doped region being surrounded in the main plane and in contact with an unintentionally doped region, or a PN junction, the first doped region being surrounded in the main plane and in contact with the second doped region.
    Preferably, the semiconductor portion is made based on germanium.
    Preferably, the peripheral piezoelectric portion is made of PZT.
    Preferably, the peripheral piezoelectric portion extends along the main plane in a manner substantially coplanar with the diode.
    DD18624 - ICG090247 The optoelectronic device can comprise a matrix of coplanar diodes, the semiconductor portions of which are electrically isolated from each other by a peripheral piezoelectric portion extending along the main plane continuously.
    The optoelectronic device may include a metallization surrounding each semiconductor portion and resting on one end of the peripheral piezoelectric portion opening onto the first face or the second face, the first circuit being adapted to apply a difference in electrical potential between the metallization and the peripheral conductive layer of each diode, so as to cause a compression deformation of the peripheral piezoelectric portion along the main plane.
    The optoelectronic device may include a second peripheral conductive layer arranged so that the peripheral piezoelectric portion is interposed, along the main plane, between the second peripheral conductive layer and said peripheral conductive layer in contact with the semiconductor portion, the first circuit being adapted to apply a difference in electrical potential between said peripheral conductive layers, so as to cause a deformation of the peripheral piezoelectric portion in the main plane in a direction opposite to the semiconductor portion.
    The invention also relates to a method for manufacturing an optoelectronic device according to any one of the preceding characteristics, comprising at least the following steps:
    realization of at least the semiconductor portion;
    conformal deposition of the peripheral conductive layer on and in contact with the lateral edge of the semiconductor portion;
    formation of the peripheral piezoelectric portion by deposition of a piezoelectric material on and in contact with one face of the peripheral conductive layer opposite the lateral border.
    BRIEF DESCRIPTION OF THE DRAWINGS Other aspects, aims, advantages and characteristics of the invention will appear better on reading the following detailed description of preferred embodiments thereof, given by way of nonlimiting example, and made with reference to the accompanying drawings in which:
    DD18624 - ICG090247 FIG. 1A is a partial and schematic view, in cross section, of an optoelectronic device according to a first embodiment in which the optoelectronic device comprises at least one diode;
    Figure 1B is a partial and schematic view, in cross section, of an optoelectronic device according to a second embodiment in which the optoelectronic device comprises a matrix of diodes;
    Figures 2A and 2B are partial and schematic top views of variants of the optoelectronic device illustrated in fig.iA, circular for one (fig.2A) and square for the other (fig.2B) , and FIG. 2C is a top view, partial and schematic, of an optoelectronic device similar to that illustrated in FIG. 2C, comprising a matrix of diodes of square shape;
    Figures 3A and 3B are partial and schematic views, in cross section, of an optoelectronic device according to two variants of the second embodiment;
    FIGS. 4A to 4N illustrate, schematically and partially, and in cross-section view, different steps of a method of manufacturing an optoelectronic device according to the second embodiment similar to that illustrated in FIG.
    DETAILED DESCRIPTION OF PARTICULAR EMBODIMENTS In the figures and in the following description, the same references represent the same or similar elements. In addition, the different elements are not shown to scale so as to favor the clarity of the figures. Furthermore, the different embodiments and variants are not mutually exclusive and can be combined with one another. Unless otherwise noted, the terms "substantially", "approximately", "in the order of" mean to the nearest 10%. Furthermore, the expression "comprising a" should be understood as "comprising at least one", unless otherwise indicated.
    The invention relates generally to an optoelectronic device comprising at least one diode, and preferably an array of diodes, each comprising a semiconductor portion surrounded, in a main plane of the diode, by a peripheral piezoelectric portion . The semiconductor portion of the diode is intended to be tensioned as a result of a deformation of the peripheral piezoelectric portion in the main plane of the diode. The peripheral piezoelectric portion is deformed by reverse piezoelectric effect. The voltage stresses undergone by the semiconductor portion then result in a modification of the optical properties and / or
    DD18624 - ICG090247 electric diode, such as a broadening of the spectral range of absorption of light radiation in the case of a photodiode. Stressing in tension may also be sufficient to make the energy band structure of the semiconductor compound substantially direct, in the case where the latter has an indirect band structure when it is in the relaxed state. The performance of the optoelectronic device can then be improved, in particular in the case of a light emitting diode.
    By constrained portion means a portion made of a crystalline semiconductor compound undergoing mechanical stress in tension or in compression, causing a deformation of the meshes of its crystal lattice. The portion is stressed in tension when it undergoes a mechanical stress which tends to stretch the meshes of the network in a plane. In the context of the invention, the semiconductor portion is intended to be voltage-constrained in a main plane of the diode. This results in the fact that its lattice parameter, in the main plane, has a so-called effective value greater than its natural value when the semiconductor compound is relaxed (i.e. unconstrained). In the following description, unless otherwise indicated, the stress considered is oriented in the main plane of the diode.
    The semiconductor compound, then subjected to mechanical stresses in voltage, therefore has modified optical and / or electrical properties. In particular, it can have a reduced band gap energy, in particular that associated with the Γ valley (or direct valley). The band gap energy can be estimated as a function of the voltage strain, as described in the case of a germanium layer in the publication by Guilloy et al. titled Germanium under high tensile stress: Nonlinear dependence of direct band gap vs strain, ACS Photonics 2016,3,1907-1911. Furthermore, the mechanical stress in tension undergone by the semiconductor portion may be sufficient for the energy band structure to become direct.
    By direct or substantially direct band structure is meant that the minimum energy Ebc.l of the conduction band of the valley L (or indirect valley) is greater than or substantially equal to the minimum energy E B c , r of the conduction band of the valley Γ (or direct valley), in other words: ΔΕ = Ebc.l - E B c, r> o. By substantially equal is meant here that this energy difference is of the order of magnitude or less than kT, where k is the Boltzmann constant and T the temperature of the material. Preferably, the semiconductor portion is produced on the basis of germanium, the structure of energy bands of which is indirect in the relaxed state, in other words ΔΕ <o, and becomes direct when it undergoes a sufficient voltage deformation.
    DD18624 - ICG090247 As detailed below, the tensioning of the semiconductor portion is obtained as a result of the deformation of the peripheral piezoelectric portion by reverse piezoelectric effect, in the main plane of the diode. By reverse piezoelectric effect is meant the physical phenomenon of deformation of the crystal structure of the piezoelectric material, in expansion or in compression, in response to the application of an electric field passing through it. In a known manner, the field T of the stresses undergone by the piezoelectric material depends on the electric field E and the piezoelectric coefficient e, and the stress tensor [T] is equal to - [e] [E].
    Figure 1A is a partial and schematic view, in cross section, of an optoelectronic device i according to a first embodiment. In this example, the optoelectronic device i comprises at least one germanium photodiode 2 adapted to detect light radiation in the near infrared (SWIR, for Short Wavelength IR, in English) corresponding to the spectral range going from 0, 8pm to i, Around 7pm or even around 2.5pm. As detailed below, the tensioning of the diode 2 is ensured by an expansion of the peripheral piezoelectric portion 30, in the main plane of the diode, in a direction opposite to the semiconductor portion 20.
    We define here and for the remainder of the description a three-dimensional direct coordinate system (Χ, Υ, Ζ), where the axes X and Y form a plane parallel to the main plane of the diode or diodes 2 of the optoelectronic device 1, and where the axis Z is oriented along the thickness of the semiconductor portion 20.
    The optoelectronic device 1 comprises at least one diode 2 with PN or PIN junction, the semiconductor portion 20 of which is surrounded by a peripheral piezoelectric portion 30. It also includes an electrical circuit for biasing the peripheral piezoelectric portion 30 intended to generate , in the first embodiment, a deformation of the peripheral piezoelectric portion 30 in the main plane of the diode 2 and in a direction opposite to the semiconductor portion 20. Consequently, the latter undergoes a mechanical stress in tension in the same plane main. It also includes an electrical circuit for biasing the diode 2.
    The semiconductor portion 20 extends along a main plane, here parallel to the XY plane, and has a first face 21 and a second opposite face 22, which are substantially parallel to the XY plane. They are connected to each other by a lateral border 23 which laterally delimits the semiconductor portion 20 in the XY plane. In this example, the first and second faces 21, 22 are substantially planar, so that the semiconductor portion 20 has a substantially homogeneous thickness. The lateral border 23 here advantageously extends parallel to the Z axis, that is to say that it is
    DD18624 - ICG090247 substantially orthogonal to the XY plane. As illustrated in fig.2A and 2B, the semiconductor portion 20 can have various shapes in the XY plane, for example circular (fig.2A) or square (fig.2B). Other forms are possible.
    The semiconductor portion 20 is produced based on a crystalline semiconductor compound of interest, which is preferably monocrystalline. By based on, it is meant that the material is an alloy formed from at least the same chemical elements as the semiconductor compound of interest. The semiconductor portion 20 can thus be a layer or a substrate made of the same semiconductor compound of interest and have regions of different types of conductivity (homojunction) so as to form the PN or PIN junction. It can alternatively be a stack of sublayers of different semiconductor compounds (heterojunction), which are alloys of the semiconductor compound of interest.
    In general, the semiconductor compound of interest is advantageously chosen from germanium-based materials, such as germanium Ge, silicon germanium SiGe, germanium tin GeSn, and silicon germanium tin SiGeSn. Preferably, the semiconductor compound of interest has, in the absence of voltage deformation of its crystal lattice, a first value of direct band gap energy, and, when it undergoes voltage deformation, a second value less than the first value. In this example, the semiconductor portion 20 comes from a layer made of the same semiconductor compound, namely here in germanium.
    The semiconductor portion 20 has a thickness along the axis Z which can be between a few hundred nanometers and a few microns, for example between ipm and 5pm approximately. In the case of a photodiode, the thickness is chosen so as to obtain good absorption in the range of wavelengths of the light radiation to be detected. It has a transverse dimension in the XY plane which can be between a few hundred nanometers and a few tens of microns, for example between about ipm and topm.
    A PN or PIN junction is formed in the semiconductor portion 20. It is formed by two regions of the semiconductor portion 20 having different types of conductivity. More specifically, it comprises a first region 24 doped with a first type of conductivity, for example of the n type, and a second region 25 doped with a second type of conductivity opposite to the first type, for example of the p type.
    The junction can thus be of PN or PIN type. In the examples of FIGS. 1A and 3A, the junction is of the PIN type, so that the semiconductor portion 20 comprises an intrinsic region 26, that is to say unintentionally doped, which extends between and in contact with the first region 24 doped n and the second region 25 doped p. In the example of the
    DD18624 - ICG090247 fig.3B, the junction is of PN type so that the first region 24 doped n is surrounded and in contact with the second region 25 doped p.
    The first n-doped region 24 here extends along the axis Z from the first face 21 and is distant from the side border 23 in the XY plane. It thus forms an n-doped box which is flush with the first face 21 and is spaced apart by a non-zero distance from the side edge 23 as well as from the second face 22. By being flush, we mean arriving at, or extends from. The first doped region 24 thus participates in delimiting the first face 21. It is electrically isolated from the lateral border 23. The first doped region n can have doping which can be between i.io 1 and 1.10 20 at / cnrt approximately.
    The second p-doped region 25 extends from the lateral border 23 in the XY plane, preferably continuously, that is to say that it is flush with the lateral border 23 preferably over the entire periphery of the semiconductor portion 20. It extends here along the axis Z from the second face 22. It may have a substantially uniform thickness along the axis Z, as illustrated in FIG.iA, and thus flush with a lower area of the lateral border 23. As a variant, as illustrated in FIGS. 3A and 3B, the second p-doped region may have a lateral zone which is flush with the entire surface of the lateral border 23, both along the Z axis and over the entire periphery of the semiconductor portion 20. The second p-doped region 25 may have doping which can be between i.io 1 and 1.10 20 at / cnrt approximately. The second p-doped region 25 is preferably overdoped so as to present good ohmic contact with the peripheral conductive layer 40 mentioned below.
    The optoelectronic device 1 according to the first embodiment comprises two concentric peripheral conductive layers 4Ο1, 402. A first peripheral conductive layer 4Ο1 is in contact with the lateral edge 23 of the semiconductor portion 20 and is adapted to participate in the electrical polarization of the diode 2 as well as in the electrical polarization of the peripheral piezoelectric portion 30. The second conductive layer peripheral 402 is arranged so that the peripheral piezoelectric portion 30 is interposed, in the plane XY, between the two peripheral conductive layers 4Ο1, 4Ο2.
    The first peripheral conductive layer 4Ο1 extends along the main plane in contact with the second p-doped region 25 so as to surround the semiconductor portion 20. It is therefore in contact with the side edge 23 of the semiconductor portion 20, and more precisely of the second p-doped region 25 which is flush with the lateral border 23, and therefore allows the application of an electrical potential V- to the second p-doped region 25. It thus at least partially covers the lateral border 23, and
    DD18624 - ICG090247 preferably entirely as illustrated in fig.iA. It surrounds at least partially the semiconductor portion 20, and preferably entirely as illustrated in FIGS. 1B and 1C, so as to participate in making more homogeneous, along the periphery of the semiconductor portion 20, the mechanical stresses in tension undergone by the semiconductor portion 20 due to the deformation of the peripheral piezoelectric portion.
    The first peripheral conductive layer 4Ο1 is formed of one or more conductive sublayers, and is made of at least one electrically conductive material, for example TiN. Ti, NiCr, Al, Au, Pt, W, Ni, Cu, Mo etc. It preferably has a thickness that is substantially constant along its surface area, for example between approximately ton and toon. Preferably, it has a height along the axis Z at least equal to the thickness of the semiconductor portion 20, and thus entirely covers the lateral border 23 along the axis Z.
    The optoelectronic device 1 comprises a peripheral piezoelectric portion 30, adapted here to undergo deformation in the main plane of the diode 2 in a direction opposite to the semiconductor portion 20, by reverse piezoelectric effect, thus causing the formation of mechanical stresses in voltage in the semiconductor portion 20 in the main plane of the diode, that is to say in the XY plane.
    The peripheral piezoelectric portion 30 extends along the main plane in contact with the first peripheral conductive layer 4Ο1 so as to surround the semiconductor portion 20. There is therefore physical and electrical contact between the peripheral piezoelectric portion 30 and the first peripheral conductive layer 4Ο1, which is therefore suitable for applying an electrical potential to the peripheral piezoelectric layer. It thus at least partially covers the first peripheral conductive layer 4Ο1 along the axis Z, and preferably entirely as illustrated in fig.iA. It surrounds at least partially the semiconductor portion 20, and preferably entirely, as illustrated in FIGS. 1B and 1C, so as to participate in making the mechanical stresses undergone more homogeneous, along the periphery of the semiconductor portion 20 by the semiconductor portion 20 due to the deformation of the peripheral piezoelectric portion 30. It thus extends along all or part of the periphery of the semiconductor portion 20. Thus, the first peripheral conductive layer 4Ο1 is interposed, in the XY plane, between the semiconductor portion 20 and the peripheral piezoelectric portion 30.
    The peripheral piezoelectric portion 30 is formed from at least one piezoelectric material, preferably lead zirconate titanate PbZrTiO 3 (PZT), but other materials can be used, such as BaTiO 3 , AlN, ZnO , LiNbO 3 , Pb (NbO 3 ) 2 , PbTiO 3 , Pb (Mg o , 33 Nbo.66) O 3 , Pb (Sco, 5 Tao, 5 ) O 3 or any other suitable piezoelectric material.
    DD18624 - ICG090247
    The peripheral piezoelectric portion 30 preferably extends continuously around the semiconductor portion 20, so as to participate in making the mechanical mechanical stresses in tension undergone by the latter along the periphery of the semiconductor portion 20. Preferably, it has a thickness along the axis Z greater than or equal to that of the semiconductor portion 20, so as to participate in making the mechanical mechanical stresses in tension undergone by the semiconductor portion 20 substantially along the axis Z.
    The optoelectronic device 1 here comprises a second peripheral conductive layer 402, preferably made of the same material or materials as for the first peripheral conductive layer 4Ο1. It extends in contact with an external lateral flank of the peripheral piezoelectric portion 30 so as to surround the latter in the XY plane. Thus, the peripheral piezoelectric portion 30 has an internal lateral flank, oriented towards the semiconductor portion 20 and in contact with the first peripheral conductive layer 4Ο1, and an external lateral flank, opposite to the internal flank, in contact with the second peripheral conductive layer 4Ο2 .
    The optoelectronic device 1 comprises a first electrical circuit for biasing the peripheral piezoelectric portion 30, which electrical biasing makes it possible to cause deformation of the peripheral piezoelectric portion 30 in the main plane and in a direction opposite to the semiconductor portion 20. For this, the electrical circuit includes metallizations (not shown), in contact with the two peripheral conductive layers 4Ο1, 4Ο2, making it possible to apply a potential difference to the peripheral piezoelectric portion 30. The metallizations preferably rest on the first face 21 , and are in electrical contact with one end of the peripheral conductive layers 4Ο1, 4Ο2. They can be studs whose dimensions in the XY plane can be of the same order as their thickness, or be strips which extend longitudinally in contact with the peripheral conductive layers 4Ο1, 4Ο2, preferably over the entire length thereof. . A negative electrical potential V- can thus be applied to the first peripheral conductive layer 4Ο1, and a positive electrical potential Vp + can be applied to the second peripheral conductive layer 4Ο2.
    Thus, in operation, a bias voltage of the peripheral piezoelectric portion 30 is applied through the two peripheral conductive layers 4Ο1, 402, bringing the first to the electrical potential V- and the second to the electrical potential Vp +. An electric field is then generated within the peripheral piezoelectric portion 30 whose field lines extend substantially parallel to the XY plane. Due to the orientation of the peripheral conductive layers 4Ο1.4Ο2 along the axis Z along the peripheral piezoelectric portion 30,
    DD18624 - ICG090247 the electric field generated has a non-zero component in the XY plane, and thus induces a deformation in the XY plane of the peripheral piezoelectric portion 30 by reverse piezoelectric effect, in a direction opposite to the semiconductor portion 20 (represented by arrows). Insofar as the peripheral piezoelectric portion 30 surrounds the semiconductor portion 20 on the one hand, and there is material continuity between the peripheral piezoelectric portion 30 and the semiconductor portion 20 in the XY plane on the other hand, the constraints mechanical undergone by the peripheral piezoelectric portion 30 are transmitted in the semiconductor portion 20, so that the semiconductor portion 20 then undergoes mechanical stresses in voltage along the XY plane, that is to say along the main plane.
    Figure 1B is a partial and schematic view, in cross section, of an optoelectronic device 1 according to a second embodiment. In this example, the optoelectronic device 1 comprises a matrix of diodes 2 adjacent in the XY plane and substantially coplanar. The diodes 2 are here germanium photodiodes 2 adapted to detect light radiation in the near infrared. As detailed below, the tensioning of the diodes 2 is ensured by compression of the peripheral piezoelectric portion 30, in the main plane of the diode.
    The optoelectronic device 1 according to this embodiment differs from that illustrated in fig.iA essentially in that with each diode 2 is associated a peripheral conductive layer 40 interposed between the semiconductor portion 20 and the peripheral piezoelectric portion 30 The other peripheral conductive layer 40 illustrated in FIG. IB is that associated with the adjacent diodes 2. Also, the adjacent conductive layers are preferably brought to the same negative electrical potential V-. Furthermore, the piezoelectric material is chosen from electrically insulating materials, so as to provide electrical insulation between the diodes 2.
    It thus comprises a first metallization (not shown) of polarization of the peripheral conductive layer 40, preferably resting on the first face 21 of the optoelectronic device 1 and in electrical contact with one end of said peripheral conductive layer 40.
    It also includes, in this example, a second metallization 42 (illustrated in dotted lines in Fig.2C) of polarization of the peripheral piezoelectric portion 30, preferably resting on the first face 21 and in contact with the piezoelectric material. The second metallization 42 can be a plurality of studs arranged so as to surround the semiconductor portion 20, or can be a strip which extends so as to continuously surround the semiconductor portion 20. It is preferably located between each
    DD18624 - ICG090247 adjacent peripheral conductive layer 40, in the XY plane. A positive electrical potential Vp + can thus be applied to the peripheral piezoelectric portion 30 by means of this metallization.
    Thus, in operation, a bias voltage is applied to the peripheral piezoelectric portion 30, thereby generating an electric field in the peripheral piezoelectric portion 30, the field lines of which extend between the peripheral conductive layer 40 and the second metallization. 42. Due to the orientation of the peripheral conductive layer 40 along the peripheral piezoelectric portion 30 along the Z axis, the electric field generated has a non-zero component in the XY plane, and thus induces a compression deformation of the peripheral piezoelectric portion 30 in the XY plane by reverse piezoelectric effect. Insofar as the peripheral piezoelectric portion 30 surrounds the semiconductor portion 20 on the one hand, and there is material continuity between the peripheral piezoelectric portion 30 and the semiconductor portion 20 in the XY plane on the other hand, the constraints mechanical undergone by the peripheral piezoelectric portion 30 are transmitted in the semiconductor portion 20, so that the semiconductor portion 20 then undergoes mechanical stresses in voltage along the XY plane.
    The optoelectronic device 1 according to the first and second embodiments comprises a second electrical bias circuit of the diode (s) 2, so as to allow the emission or detection of light radiation.
    For this, the electrical circuit includes metallizations (not shown) for polarizing the diode (s) 2 direct or reverse, depending on the application of emission or detection of the diode. Thus, in the case of a photodiode, a first metallization is located on and in contact with the first n-doped region 24, and adapted to apply a positive electrical potential Vd-ι- to the latter. The application of a negative potential V- to the second p-doped region 25 is carried out by means of the peripheral conductive layer 40 with which it is in contact. Thus, the electrical potential applied to the peripheral conductive layer 40 makes it possible both to polarize the peripheral piezoelectric portion 30 to induce a compression deformation therein, and to polarize the diode 2 here in reverse.
    Figure 2C is a top view, schematic and partial, of an optoelectronic device 1 identical to that illustrated in fig.iB, the diodes 2 of which have a square shape. The diodes 2 are electrically isolated from each other by the peripheral piezoelectric portion 30 which here extends continuously in the XY plane. Each diode 2 has a peripheral conductive layer 40 inserted in the XY plane between
    DD18624 - ICG090247 the semiconductor portion 20 and the peripheral piezoelectric portion 30. The first electrical circuits include a metallization 42 (dotted line) of polarization of the peripheral piezoelectric portion 30, which extends longitudinally on the first face 21 around each diode 2 The metallization 42 is brought to a positive electrical potential Vp + and each peripheral conductive layer 40 is brought to a negative electrical potential V-, thus making it possible to generate an electric field in the peripheral piezoelectric portion 30 capable of causing the compression deformation of this last. Furthermore, each first region 24 doped n is brought to a positive electrical potential Vd +. Thus, each diode 2 is here reverse biased, thus allowing photodetection of the infrared light radiation. Each peripheral conductive layer 40 participates in polarizing at the same time the peripheral piezoelectric portion 30 as well as the corresponding semiconductor portion 20.
    Figure 3A is a partial and schematic view, in cross section, of a variant of the optoelectronic device 1 according to the second embodiment illustrated in fig.iA. The optoelectronic device 1 is essentially distinguished in that the second p-doped region 25 comprises a lateral zone, preferably also overdoped, which is flush with the lateral border 23 over the entire height thereof along the axis Z, and along the entire periphery of the semiconductor portion 20 in the XY plane. Thus, the polarization of the second p-doped region 25 is improved insofar as the surface of the ohmic contact with the peripheral conductive layer 40 is increased. In addition, such a configuration of the PIN junction makes it possible to prevent the space charge area between the n and p doped regions from extending to the lateral border 23. Thus, the contribution of this area is limited (potentially not free from faults linked to the construction of the trenches) in the dark current. This variant also applies to the optoelectronic device 1 according to the first embodiment.
    Figure 3B is a partial and schematic view, in cross section, of a variant of the optoelectronic device 1 according to the second embodiment illustrated in fig.3A. The optoelectronic device 1 is distinguished in particular in that the diode 2 comprises a PN junction and not a PIN junction, as could also be the case in the first embodiment of fig.iA. Furthermore, the second p-doped region 25 may include an overdoped zone which is flush with the lateral border 23 and here the second face 22, and a zone with a lower p-doping level, which surrounds the n-doped well. It is also distinguished from it in that an intermediate conductive layer 44 between the peripheral conductive layer 40 in contact with the semiconductor portion 20 considered and that in contact with the semiconductor portion 20 of a neighboring diode 2. This intermediate conductive layer 44 here extends substantially parallel to the peripheral conductive layer 40 along the axis Z, and surrounds the semiconductor portion 20 in
    DD18624 - ICG090247 the XY plane. It is brought to the positive electrical potential Vp +. Thus, the electric field generated between the intermediate conductive layer 44 and the peripheral conductive layer 40 essentially comprises a component parallel to the plane XY, which thus improves the intensity of deformation in compression of the piezoelectric material, as well as the homogeneity of deformation according to the Z axis. The semiconductor portion 20 then undergoes a voltage stress whose homogeneity along the Z axis is also improved.
    The optoelectronic device 1 then has the advantage of enabling the semiconductor portion 20 of the diode or diodes 2 to be energized in an active manner, that is to say by applying a bias voltage of the material. piezoelectric. As detailed above, the polarization of the piezoelectric material can induce a deformation of the peripheral piezoelectric portion 30 in the XY plane in a direction opposite to the semiconductor portion 20 (first embodiment illustrated in FIG. IA), or a compression deformation in the XY plane (second embodiment illustrated in fig.iB). The value of the stress in tension can be controlled in a precise and simplified way, insofar as it depends essentially on the intensity of the tension of polarization of the piezoelectric material, and not of a technology of stressing by deposit d 'A stack of thin layers or of a structuring of the semiconductor portion 20 followed by a suspension. Thus, an optoelectronic device 1 is obtained, the optical and / or electrical properties of which can be modified in a controlled manner, that is to say here actively, during the operation of the optoelectronic device 1, by modulating the bias voltage of the piezoelectric material. It is then possible to widen the absorption spectral range of the optoelectronic device 1, for example up to a cutoff wavelength greater than i550nm in the case of a germanium photodiode 2. It is also possible, notably in the context of a telecom application, to modulate the signal to noise ratio associated with the photodiode, by varying the bias voltage of the piezoelectric material.
    In addition, the optoelectronic device 1 has a small footprint, insofar as the peripheral piezoelectric portion 30 extends substantially coplanar with the semiconductor portion 20 of the diode (s) 2. The piezoelectric material essentially covers the border lateral 23 of the semiconductor portion 20 and preferably does not coat the first face 21 and / or the second face 22 of the diode. Such an arrangement of the peripheral piezoelectric portion 30 relative to the diodes 2 also allows a high spatial density of diodes 2, and therefore a high
    DD18624 - ICG090247 spatial resolution of the optoelectronic device 1, in the case where the latter comprises a matrix of diodes 2.
    For example, the optoelectronic device i may include a photodiode 2, the semiconductor portion 20 of which is circular and made of germanium. The first n-doped region 24 may have a diameter of approximately 3 μm and the semiconductor portion 20 may have a diameter of approximately 8 μm. It is bordered by a peripheral piezoelectric portion 30 in ΡΖΓ with a transverse dimension of approximately ipm. A peripheral conductive layer 40 of TiN is interposed between the peripheral piezoelectric portion 30 and the peripheral conductive layer 40. A study by numerical simulation has made it possible to show that a bias voltage of the peripheral piezoelectric portion 30 of approximately + 5V makes it possible to cause a deformation of 0.5nm in the XY plane of the semiconductor portion 20. Such a constraint then makes it possible to increase the cut-off wavelength of the germanium in voltage to a value greater than 1550nm.
    An example of a method for manufacturing an optoelectronic device 1 according to the second embodiment identical or similar to that illustrated in FIG. IB is now described with reference to FIGS. 4A to 4N. In this example, the diodes 2 are photodiodes with PIN junctions made of germanium and are suitable for detecting infrared radiation in the SWIR range.
    In a first step (fig.4A), a first semiconductor sublayer 12.1 of monocrystalline germanium is produced. The first semiconductor sublayer 12.1 is secured to a support layer 10, here made of silicon, by means of a lower dielectric layer 11, here made of a silicon oxide. This stack takes the form of a GeOI substrate (for Germanium On Insulator, in English). This stacking is preferably carried out by means of the method described in the publication of Rebond et al. titled Structural and optical properties of 200mm germanium-on-insulator (GeOI) substrates for silicon photonics applications, Proc. SPIE 9367, Silicon Photonics X, 936714 (February 27, 2015). Such a method has the advantage of producing a 12.1 semiconductor sublayer of germanium having a low rate of structural defects such as dislocations. The germanium can be unintentionally doped or be doped, for example of the p type. The semiconductor underlayer 12.1 may have a thickness of between about loonm and 5oonm, for example equal to about 3oonm, and may be covered with a protective layer (not shown) of a silicon oxide.
    In a next step (fig.4B), doping of the first germanium sublayer 12.1 is carried out according to the second type of conductivity, here of type p, by implantation
    DD18624 - ICG090247 ionic dopant such as boron. The protective layer, if any, has been previously removed by surface cleaning, and the first germanium sub-layer 12.1 can be coated with a pre-implantation oxide layer with a thickness of a few tens of nanometers, for example equal to 2onm. The germanium sublayer 12.1 then has a doping level of between 1.10 19 and 1.10 20 at / cm 3 approximately. A diffusion annealing of the dopant can then be carried out under nitrogen, for a few minutes to a few hours, for example 1 h, at a temperature which may be between 6oo ° C. and 8oo ° C., for example equal to 8oo ° C. This step makes it possible to obtain an overdoping of the germanium sublayer 12.1 improving the ohmic contact between the second p-doped region 25 and the peripheral conductive layer 40.
    In a next step (fig.4C), a second semiconductor sublayer 12.2 of germanium is produced by epitaxy from the first sublayer 12.1. The two sublayers are intended to form the semiconductor portions 20 of germanium of the diode array 2. The second sublayer 12.2 is formed by epitaxy, for example by chemical vapor deposition (CVD, for Chemical Vapor Deposition, in English) or by any other epitaxy technique. The pre-implementation oxide layer, if any, has been previously removed by surface cleaning. The second germanium sublayer 12.2 is here intrinsic, that is to say unintentionally doped. It is intended to form the light absorption zone of diodes 2. Its thickness depends on the range of wavelengths of light radiation to be detected in the case of a photodiode. In the context of 2 SWIR photodiodes, the sub-layer 12.2 of intrinsic germanium has a thickness for example of between ipm and 3pm, preferably equal to i, 5pm.
    In a next step (fig.4D), a localized etching of the germanium semiconductor layer formed of the two sub-layers is carried out in order to form a continuous trench 14 in the XY plane ensuring the pixelation of the diodes 2. For this, an upper dielectric layer 13 is preferably deposited beforehand on the exposed face of the semiconductor layer. The upper dielectric layer 13 may have a thickness of a few tens to a few hundred nanometers, for example between 2 μm and 3 μm approximately, for example equal to approximately μm. The realization of the trench 14 is carried out by conventional photolithography and etching techniques. This etches a localized area of the upper dielectric layer 13, of the second sublayer 12.2 of intrinsic germanium and at least part of the thickness of the first sublayer 12.1 of overdoped germanium. A plurality of germanium semiconductor portions 20 are thus obtained, separated from each other by the continuous trench 14. The trench 14 is preferably obtained by an anisotropic etching technique, so as to obtain a lateral border 23 of the portions
    DD18624 - ICG090247 semiconductor 20 substantially planar along the Z axis, and preferably substantially orthogonal to the XY plane. The continuous trench 14 has a transverse dimension (width) in the XY plane which can be between 300nm and 30pm, for example between ipm and 2pm approximately. It extends longitudinally in the XY plane so as to delimit the semiconductor portions 20. The latter can thus have a shape in the XY plane, for example circular, oval, polygonal, for example square, or any other shape.
    In this example, the first sub-layer 12.1 is locally etched over its entire thickness to lead to the lower dielectric layer 11. As a variant (not shown), the first sub-layer 12.1 can be locally etched in part, from so as to keep a continuous lower portion of overdoped germanium, in order to increase the ohmic contact surface between the second p-doped region 25 and the peripheral conductive layer 40.
    To obtain a second p-doped region 25 which includes a lateral zone extending along the lateral border 23 along the Z axis, and around the periphery of the semiconductor portion 20 in the XY plane, as illustrated in the fig-3A and 3B, an additional ion implantation, for example of boron, can be performed with a non-zero angle of inclination, so as to boost the lateral flank of the semiconductor portions 20.
    In a next step (fig.4E), a continuous conductive layer 15 is deposited conformally on the exposed surface of the structure obtained above. The conductive layer is made of at least one electrically conductive material, here made of TiN. It can be deposited by chemical vapor deposition (CVD) and continuously covers the lateral border 23 of the semiconductor portions 20, as well as the upper dielectric layer 13 and here the exposed surface of the lower dielectric layer 11. This continuous conductive layer 15 is intended to form the peripheral conductive layers which extend in contact with the lateral edge 23 in order to ensure the joint polarization of the second p-doped region 25 and of the peripheral piezoelectric portion 30. The continuous conductive layer 15 may have a thickness between tonm and toonm approximately.
    In a next step (fig.4F), the peripheral piezoelectric portion 30 is produced. For this, a deposition of a piezoelectric material, for example here of ΡΖΓ, is carried out so as to continuously cover the structure obtained beforehand and therefore filling the trench 14. The piezoelectric material is then in contact with the continuous conductive layer. It can be deposited by physical vapor deposition (PVD, for Physical Vapor Deposition, in English) or by any other suitable technique. The conductive layer
    DD18624 - ICG090247 peripheral 40, especially when it is made of TiN, ensures good grip for the piezoelectric material, especially when it is in ΡΖΓ. The piezoelectric material is preferably dielectric, thus ensuring electrical isolation between the photodiodes
    2. An annealing step can be implemented, for example between 3OO ° C and 7OO ° C, to optimize the piezoelectric properties of the material. A planarization step, for example mechanical-chemical (CMP), is then implemented, with stopping on the upper part of the continuous conductive layer.
    In a following step (FIG. 4G), zones of ion implantation of dopants are defined in order to form the first n-doped regions 24. For this, a photosensitive resin 16 is deposited, the openings 17 of which are located opposite the semiconductor portion 20. Then localized etching of an upper zone of the continuous conductive layer 15 and preferably of part of the layer upper dielectric 13. The transverse dimensions, in the XY plane, of the localized etching correspond substantially to that of the first n-doped regions 24 that it is desired to obtain. These transverse dimensions thus depend on those of the semiconductor portion 20, and can be understood, for example, between 3oonm and topm.
    In a following step (FIG. 4H), the first n-doped portions are produced by ion implantation of a dopant such as phosphorus, through the openings 17. The first regions 24 are preferably overdoped, and may thus have a doping level of between 1.10 19 and 1.10 20 at / cnU approximately. The first n-doped regions 24 thus form n-doped wells delimited in the XY plane and in the direction -Z by the second sublayer 12.2 of intrinsic germanium. A resistive contact is thus formed at the interface between the peripheral conductive layer 40 and the intrinsic germanium of the second sublayer 12.2. A diffusion annealing of the dopants can be carried out, for example at a temperature between 4OO ° C and 7OO ° C for a period of a few seconds to a few tens of minutes, for example at 6oo ° C for 30s.
    In the following steps (fig. 41 and 4J), an additional dielectric layer 18 is deposited in order to then carry out the polarization metallizations. For this, the photosensitive resin 16 is removed and then a dielectric layer is deposited (FIG. 41), for example made of a silicon oxide or a tetraethyl orthosilicate (TEOS), so as to completely cover the structure obtained previously. The dielectric layer 18 may have a thickness of between 50 nm and 2 μm, for example. First, through photolithography and etching, 19.1 openings are made in the dielectric layer (FIG. 4J) with etching stop on the peripheral conductive layer 40, with a view to forming the polarization metallizations 41 of the peripheral conductive layer. The openings thus open onto an upper zone
    DD18624 - ICG090247 of the peripheral conductive layer 40 which extends over the upper dielectric layer
    13. Second through openings 19.2 are also produced in order to form metallizations 42 of polarization of the peripheral piezoelectric portion 30, and third openings 19.3 in order to form metallizations 43 of polarization of the first n-doped regions 24. The second openings 19.2 can extend longitudinally so as to surround each diode 2 in the XY plane. In other words, each diode 2 is surrounded by the same second opening 19.2 which can extend longitudinally continuously or even discontinuously. The openings 19.1, 19.2, 19.3 may have transverse dimensions in the XY plane of between a few hundred nanometers and a few microns, depending on the dimensions of the diodes 2 and the width of the peripheral piezoelectric portion 30.
    In a next step (fîg.qK), the metallizations 41, 42, 43 are made through the through openings 19.1,19.2,19.3. The metallizations 41, 42, 43 are made of at least one metallic material, and can be formed of a barrier layer, for example of TiN deposited by CVD, followed by a layer of copper. A planarization step, for example by CMP, is then carried out with etching stop on the upper layer of protective oxide.
    In a next step (fig.qL), the mechanical and electrical assembly, also called hybridization, is then carried out of the structure thus obtained to a control chip 3. The hybridization can be carried out by direct bonding (or bonding by molecular adhesion, direct bonding, in English) of copper / copper type and / or of oxide / oxide type, or by any other hybridization technique.
    In a following step (fig.qM), the silicon support layer 10 is advantageously removed, for example by grinding (grinding) and / or by wet etching or by plasma dry etching ( RIE, ICP ...), with etching stop on the lower dielectric layer 11. It is also possible to perform localized etching of the lower dielectric layer 11 as well as the continuous conductive layer, so as to expose one face of the peripheral piezoelectric portion 30. Thus, the lower dielectric layer 11 ensures the passivation of the semiconductor portion 20.
    In a next step (fig.qN), it is possible to remove the remaining lower dielectric layer 11, so as also to expose the second face 22 of the semiconductor portion 20, and then to deposit a dielectric layer 4 at least partially transparent. This layer 4 provides protection for the diodes 2, the passivation of the second face 22 of the semiconductor portions 20, and can also provide an optical anti-reflection function when its thickness is a multiple of λ / 4η, where λ is a length of wave of the light radiation to be detected and n is the refractive index of the material of the
    DD18624 - ICG090247 anti-reflective coating. Such a layer 4 can be made of an oxide or a nitride of silicon, for example Si0 2 , SiN, Si 3 N 4 , or of aluminum, for example AIN or A1 2 O 3 . Its thickness can be, for example, between 2onm and 2oonm approximately.
    Thus, this manufacturing method makes it possible to obtain an optoelectronic device 1 comprising a matrix of diodes 2, the semiconductor portions 20 of which can be actively tensioned, that is to say by the application of a potential difference at the peripheral piezoelectric portion 30 surrounding each diode, resulting in the deformation of the latter. Furthermore, the optoelectronic device 1 can have a high spatial resolution, as well as a small footprint, insofar as the peripheral piezoelectric portion 30 extends coplanarly with the diodes 2. In addition, the peripheral piezoelectric portion 30 defines, with the diodes 2, a substantially planar optoelectronic structure, delimited along the axis Z by two substantially planar faces, which contributes to reducing the size of the optoelectronic device 1. Furthermore, the diodes 2 have good optical properties and / or electronic, in particular insofar as any structural defects such as dislocations remain confined essentially in the second p-doped region 25 and not in the intrinsic region 26.
    Furthermore, it is advantageous that the first regions 24 are n-doped and that the second regions 25 are p-doped in terms of duration of diffusion annealing. Indeed, the boron used for p doping diffuses more slowly than the phosphorus used for n doping. Thus, the diffusion annealing of phosphorus, which requires a short duration, is carried out after the diffusion annealing of boron, which requires a longer duration.
    Particular embodiments have just been described. Different variants and modifications will appear to those skilled in the art.
    权利要求:
    Claims (15)
    [1" id="c-fr-0001]
    1. Optoelectronic device (1), comprising:
    o at least one diode (2), comprising a semiconductor portion (20) having:
    • a first face (21) and a second face (22) opposite, substantially parallel to a main plane, and connected to each other by a lateral border (23), and • a PN or PIN junction formed by:
    a first region (24) doped according to a first type of conductivity, and a second region (25) doped according to a second type of conductivity opposite to the first type, extending from the lateral border (23);
    o a peripheral conductive layer (40), made of at least one electrically conductive material, extending along the main plane in contact with the second doped region (25) so as to surround the semiconductor portion (20);
    o a peripheral piezoelectric portion (30), made of at least one piezoelectric material, extending along the main plane in contact with the peripheral conductive layer (40) so as to surround the semiconductor portion (20);
    a first electric circuit for biasing the peripheral piezoelectric portion (30), adapted to generate an electric field in the peripheral piezoelectric portion (30) by applying an electrical potential to at least the peripheral conductive layer (40), so as to induce a deformation of the peripheral piezoelectric portion (30) oriented along the main plane then causing a voltage deformation of the semiconductor portion (20) along the main plane.
    [2" id="c-fr-0002]
    2. Optoelectronic device (1) according to claim 1, wherein the peripheral conductive layer (40) and the peripheral piezoelectric portion (30) surround the semiconductor portion (20) continuously.
    [3" id="c-fr-0003]
    3. Optoelectronic device (1) according to claim 1 or 2, wherein the peripheral conductive layer (40) entirely covers the lateral edge (23) of the semiconductor portion (20) along an axis orthogonal to the main plane, and the piezoelectric portion peripheral (30) entirely covers the peripheral conductive layer (40) along said orthogonal axis.
    [4" id="c-fr-0004]
    4. Optoelectronic device (1) according to any one of claims 1 to 3, wherein the side edge (23) extends substantially orthogonal to the main plane.
    DD18624 - ICG090247
    [5" id="c-fr-0005]
    5- Optoelectronic device (i) according to any one of claims i to 4, in which the peripheral piezoelectric portion (30) has a thickness at least equal to that of the semiconductor portion (20).
    [6" id="c-fr-0006]
    6. Optoelectronic device (1) according to any one of claims 1 to 5, comprising a second electrical circuit for biasing the diode (2), adapted to apply said electrical potential to the second doped region (25) by means of the peripheral conductive layer (40) and a different electrical potential to the first doped region (24).
    [7" id="c-fr-0007]
    7. Optoelectronic device (1) according to any one of claims 1 to 6, in which the first doped portion (24) extends from the first face (21) and is distant from the lateral border (23).
    [8" id="c-fr-0008]
    8. Optoelectronic device (1) according to any one of claims 1 to 7, in which the diode (2) comprises:
    - a PIN junction, the first doped region (24) being surrounded in the main plane and in contact with an unintentionally doped region (26), or
    - A PN junction, the first doped region (24) being surrounded in the main plane and in contact with the second doped region (25).
    [9" id="c-fr-0009]
    9. Optoelectronic device (1) according to any one of claims 1 to 8, in which the semiconductor portion (20) is made based on germanium.
    [10" id="c-fr-0010]
    10. Optoelectronic device (1) according to any one of claims 1 to 9, in which the peripheral piezoelectric portion (30) is made in ΡΖΓ.
    [11" id="c-fr-0011]
    11. Optoelectronic device (1) according to any one of claims 1 to 10, in which the peripheral piezoelectric portion (30) extends along the main plane in a manner substantially coplanar with the diode (2).
    [12" id="c-fr-0012]
    12. Optoelectronic device (1) according to any one of claims 1 to 11, comprising an array of coplanar diodes (2), the semiconductor portions (20) of which are electrically isolated from one another by a peripheral piezoelectric portion (30) extending along the main plane continuously.
    [13" id="c-fr-0013]
    13. Optoelectronic device (1) according to claim 12, comprising a metallization (42) surrounding each semiconductor portion (20) and resting on one end of the peripheral piezoelectric portion (30) opening onto the first face (21) or the second face (22), the first circuit being adapted to apply a difference of
    DD18624 - ICG090247 electrical potential between the metallization (42) and the peripheral conductive layer (40) of each diode (2), so as to cause a compression deformation of the peripheral piezoelectric portion (30) along the main plane.
    [14" id="c-fr-0014]
    14. Optoelectronic device (1) according to any one of claims 1 to 12, comprising a second peripheral conductive layer (402) arranged so that the peripheral piezoelectric portion (30) is interposed, along the main plane, between the second layer peripheral conductor (402) and said peripheral conductive layer (4Ο1) in contact with the semiconductor portion (20), the first circuit being adapted to apply a difference in electrical potential between said peripheral conductive layers (4Ο1, 4O 2 ), so as to causing a deformation of the peripheral piezoelectric portion (30) in the main plane in a direction opposite to the semiconductor portion (20).
    [15" id="c-fr-0015]
    15. Method for manufacturing an optoelectronic device (1) according to any one of the preceding claims, comprising at least the following steps:
    - production of at least the semiconductor portion (20);
    - conformal deposition of the peripheral conductive layer (40) on and in contact with the lateral edge (23) of the semiconductor portion (20);
    - Formation of the peripheral piezoelectric portion (30) by deposition of a piezoelectric material on and in contact with one face of the peripheral conductive layer (40) opposite the side edge (23).
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    同族专利:
    公开号 | 公开日
    US20210111205A1|2021-04-15|
    CN112055895A|2020-12-08|
    WO2019202250A1|2019-10-24|
    EP3782205A1|2021-02-24|
    FR3080489B1|2020-05-08|
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    US20090108387A1|2007-10-30|2009-04-30|Nathaniel Quitoriano|Semiconductor Device And Method For Strain Controlled Optical Absorption|
    US20150308891A1|2012-11-29|2015-10-29|International Business Machines Corporation|Optical spectrometer|US10854646B2|2018-10-19|2020-12-01|Attollo Engineering, LLC|PIN photodetector|US9780248B2|2012-05-05|2017-10-03|Sifotonics Technologies Co., Ltd.|High performance GeSi avalanche photodiode operating beyond Ge bandgap limits|
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    法律状态:
    2019-04-29| PLFP| Fee payment|Year of fee payment: 2 |
    2019-10-25| PLSC| Publication of the preliminary search report|Effective date: 20191025 |
    2020-04-30| PLFP| Fee payment|Year of fee payment: 3 |
    2022-01-07| ST| Notification of lapse|Effective date: 20211205 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1853386A|FR3080489B1|2018-04-18|2018-04-18|OPTOELECTRONIC DEVICE WITH A VOLTAGE-CONSTRAINED DIODE BY REVERSE PIEZOELECTRIC EFFECT|
    FR1853386|2018-04-18|FR1853386A| FR3080489B1|2018-04-18|2018-04-18|OPTOELECTRONIC DEVICE WITH A VOLTAGE-CONSTRAINED DIODE BY REVERSE PIEZOELECTRIC EFFECT|
    EP19744752.7A| EP3782205A1|2018-04-18|2019-04-15|Optoelectronic device having a diode put under tensile stress by an inverse piezoelectric effect|
    US17/044,510| US20210111205A1|2018-04-18|2019-04-15|Optoelectronic device having a diode put under tensile stress by an inverse piezoelectric effect|
    PCT/FR2019/050882| WO2019202250A1|2018-04-18|2019-04-15|Optoelectronic device having a diode put under tensile stress by an inverse piezoelectric effect|
    CN201980026320.5A| CN112055895A|2018-04-18|2019-04-15|Optoelectronic device with diode under tensile stress due to inverse piezoelectric effect|
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